1. Field of the Invention
The present invention relates to semiconductor integrated circuit fabrication. More particularly, the present invention relates to a method of fabricating on-chip inductors over an insulating layer with low permitivity or high permeability to decrease both parasitic capacitance and mutual inductance.
2. Description of the Related Art
Miniaturization of electronic circuits is a goal in virtually every field, not only to achieve compactness in mechanical packaging, but also to decrease the cost of manufacturing the circuits. Many digital and analog circuits, including high-capacity memory devices, high-level microprocessors and operational amplifiers, have been successfully implemented in silicon based integrated circuits (ICs). These circuits typically include active devices such as bipolar junction transistors (BJTs) and field effect transistors (FETs), diodes of various types, and passive devices such as resistors and capacitors.
One area that remains a challenge to miniaturization is radio frequency (RF) circuitry, such as that used in cellular telephones, wireless modems, and other types of communication equipment. The problem is the difficulty producing a good inductor in silicon-based integrated circuits that is suitable for RF applications. Attempts to integrate inductors into silicon-based circuits have yielded either inductors of low quality factor (hereinafter, Q value) and high loss, or required special metalization layers such as gold.
Ewen et al. in U.S. Pat. No. 5,446,311 has disclosed a process for manufacturing high-Q inductors without using a noble metal such as gold. The process involves forming multiple metal layers with identical spiral patterns stacked up on an insulating layer to construct an inductor. Such multiple metal layers can decrease series resistance, thus increasing the Q value. The lump-sum equivalent circuit is as shown in FIG. 1. In FIG. 1, C.sub.d indicates the parasitic capacitances between the metal layers, L.sub.1 is the inductance, R.sub.s is the series resistance of the spiral metal layers, and C.sub.1 and C.sub.2 are the parasitic capacitance between the substrate and the metal layers. If the semiconductor substrate is made of a lossy material such as silicon, then R.sub.1 and R.sub.2 indicate the parasitic resistances connected in parallel with C.sub.1 and C.sub.2, respectively. Since the semiconductor substrate is usually grounded, R.sub.1, R.sub.2, C.sub.1, and C.sub.2 are grounded at one end. In addition, L.sub.2 designates the inductance in the substrate induced by the mutual inductance effect, and R.sub.SUB denotes the parasitic resistance spread over the substrate.
In semiconductor techniques, silicon oxide (SiO.sub.x) is the most common insulating material, having a relatively high relative permitivity (or dielectric constant) between 3.9 and 4.5. Therefore, in U.S. Pat. No. 5,446,311, though the Q value is increased by the multiple metal layers, the high permitivity of the silicon oxide decreases the self-resonant frequency of the inductor, thus limiting the application of the inductor to high frequency.
Abidi et al., in U.S. Pat. No. 5,539,241, have disclosed an inductor which is formed in an oxide layer overlying a silicon substrate in which the silicon material underneath the inductor is selectively removed to form a pit so as to space the inductor away from the underlying silicon substrate. In the illustrated embodiment, the silicon beneath the inductor is removed by etching, leaving the inductor suspended on the oxide layer overlying the substrate. The pit beneath the inductor is filled with an insulating medium such as air so that the parasitic capacitance of the inductor is substantially reduced and yet retains a relatively large self-resonant frequency on the order of 2 GHz or more. However, the etching of the substrate makes the whole process more complicated and incompatible with BiCMOS or CMOS standard processes.